package chipyard_learning.parameters

import chisel3._
import org.chipsalliance.cde.config._

// case object WIDTH extends Field[Int]
// case object PA extends Field[Int]
case object DWIDTH extends Field[Int]

class MyConfigHere extends Config((site, here, up) =>
  {
    case WIDTH => 8
    case DWIDTH => 2 * here(WIDTH)
  }) 

class ModuleA_here (port_width: Int)(implicit p:Parameters) extends Module{
  val width: Int = p(DWIDTH)
  val io = IO(new Bundle{
    val port_d = Input(UInt(port_width.W))
    val port_e = Output(UInt(port_width.W))
  })
  io.port_e := io.port_d + width.U
  // io.port_e := io.port_d + p(PA).U
}

class HelloWorldHere (implicit p:Parameters) extends Module {
  val width: Int = p(WIDTH)
  val io = IO(new Bundle{
    val port_a = Input(UInt(width.W))
    val port_b = Input(UInt(width.W))
    val port_c = Output(UInt(width.W))
  })
  val m_module_a = Module(new ModuleA_here(width)(p.alterPartial({
    case WIDTH => 4
    case PA => 5
  })))
  m_module_a.io.port_d := io.port_b
  io.port_c := m_module_a.io.port_e + io.port_b
}

object HelloWorldHere extends App{
  implicit val parames: Config = (new MyConfigHere).toInstance
  (new chisel3.stage.ChiselStage).emitVerilog(new HelloWorldHere()(parames), Array("--target-dir", "verilog/output"))
}


